1. Field of the Invention
This invention relates generally to semiconductor integrated circuits and, more particularly, to high-speed input circuits.
2. Description of Related Art
In modem high frequency integrated circuits, the valid data window in which signal inputs are valid for sampling by a clock is continually shrinking as system clock frequencies continue to increase. For example, modern Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) may have many communication signals, such as control inputs, data inputs, and address inputs that must be synchronously sampled by some form of high-speed clock signal.
The valid data window of a signal, defined from an output driver perspective is the period of time a signal may be valid after factoring in variable system parameters, such as process, temperature, voltage, and output loading. This valid data window is generally expressed in terms of a minimum propagation delay and a maximum propagation delay. The required data window, or sampling window, from an input sampling perspective is defined by the required time that the signal must be valid at the sampler prior to arrival of an active edge of the clock (i.e., setup time) and the required time that the signal must be held valid at the sampler after the active edge of the sampling clock (i.e., hold time). The valid data window and the sampling window combine to constrain the maximum operating frequency of a system. Reducing the sampling window will allow higher clock frequencies and allow more tolerance in system design parameters.
Once data signals and clock signals enter a semiconductor device, any divergence between how the signals are treated prior to arriving at a sampler, such as a flip-flop, widen the sampling window due to delay differences caused by buffers, routing, process, temperature and voltage variations. This is particularly true with clock signals, which may have large fan-out loads and require significant buffering to drive those loads. To compensate for the delay introduced by this clock buffering, many systems employ a Phase Locked Loop (PLL), or Delay Locked Loops (DLL) to remove any clock delay inserted by the clock buffering. These systems work well but are too complicated for many situations.
Conventionally, a sampling circuit 90 that does not incorporate a PLL or DLL may be similar to that shown in FIG. 1. In FIG. 1, a differential buffer 40 sensing transitions on an input clock 2 and an inverted input clock 4 generates an internal clock 12. The differential buffer 40 is used to enhance detection of a transition point by comparing the voltage on the input clock 2 to the voltage on the inverted input clock 4. A bus of data inputs 6 signals, D0 through Dn, is passed through a set of differential buffers 10, one for each data input 6, used for sensing transitions on the data inputs 6. The differential buffers 10 include one input connected to a voltage reference signal 8. The use of differential buffers 10 allows for faster sensing of input signal transitions, and lower voltage swings on the data inputs 6. The voltage reference signal 8 allows setting a voltage value where the transition is considered to have occurred.
After the differential buffers 10, the sensed data signals may pass through matched delays 50. Conventionally, these matched delays 50 may include active delay components, such as inverters, or may simply be metal routing lines used to delay the signal before arrival at the flip-flops 60. These matched delays 50 may be used to delay the signal by an amount similar to the delay on the internal clock 12.
By incorporating the differential buffers 10 and 40 and matched delays 50, the FIG. 1 embodiment of a sampling circuit 90 reduces the sampling window. However, as clock rates continue to increase, new circuitry and methods are needed to accurately receive and sample these communication signals with even smaller sampling windows.
There is a need for an apparatus and method that will reduce the sampling window required to accurately sample input signals without requiring complex PLL or DLL circuitry and, as a result, be capable of operation at higher clock frequencies and allow more tolerance in system designs.